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mosel vitelic 1 v55c2128164v(t/b) 128mbit low-power sdram 2.5 volt, tsop ii / bga package 8m x 16 v55c2128164v(t/b) rev. 1.2 august 2002 preliminary 67pc78pc10 system frequency (f ck ) 166 mhz 143 mhz 143 mhz 125 mhz 100mhz clock cycle time (t ck3 ) 6 ns 7 ns 7 ns 8 ns 10 ns clock access time (t ac3 ) cas latency = 3 5.4 ns 5.4 ns 5.4 ns 6 ns 7 ns clock access time (t ac2 ) cas latency = 2 5.4 ns 5.4 ns 6 ns 6 ns 8 ns clock access time (t ac1 ) cas latency = 1 19 ns 19 ns 19 ns 19 ns 22 ns features 4 banks x 2mbit x 16 organization high speed data transfer rates up to 166 mhz full synchronous dynamic ram, with all signals referenced to clock rising edge single pulsed ras interface data mask for read/write control four banks controlled by ba0 & ba1 programmable cas latency:1, 2, 3 programmable wrap sequence: sequential or interleave programmable burst length: 1, 2, 4, 8, full page for sequential type 1, 2, 4, 8 for interleave type multiple burst read with single write operation automatic and controlled precharge command random column address every clk (1-n rule) power down mode and clock suspend mode deep power mode auto refresh and self refresh refresh interval: 4096 cycles/64 ms available in 54-ball fbga, with 9x6 ball array with 3 depupulated rows, 9x8 mm and 54 pin tsop ii vdd=2.5v, vddq=1.8v programmable power reduction feature by par- tial array activation during self-refresh operating temperature range commercial ( 0 c to 70 c) extended (-25 c to +85 c) device usage chart operating temperature range package outline access time (ns) temperature mark t/b 6 7pc 7 8pc 10 0 c to 70 c ? commercial -25 c to 85 c extended
2 v55c2128164v(t/b) rev.1.2 august 2002 mosel vitelic v55c2128164v(t/b) 60 pin wbga pin configuration top view description pkg. pin count bga b 54 v 55 c 2 12816 4 s x b mosel vitelic manufactured low power synchronous dram c=cmos family 2.5v supply voltage 128mb(4k refresh) 4 banks s=sstl component rev level component package device number speed 6 ns 7 ns 8 ns a = 0.14um 10 ns pin configuration for x16 devices: < top-view > 123 789 vss dq15 vssq a vddq dq0 vdd dq14 dq13 vddq b vssq dq2 dq1 dq12 dq11 vssq c vddq dq4 dq3 dq10 dq9 vddq d vssq dq6 dq5 dq8 nc vss e vdd ldqm dq7 udqm clk cke f cas ras we nc a11 a9 g ba0 ba1 cs a8 a7 a6 h a0 a1 a10 vss a5 a4 j a3 a2 vdd
3 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) 54 pin plastic tsop-ii pin configuration top view pin names v cc i/o 1 v ccq i/o 2 i/o 3 v ssq i/o 4 i/o 5 v ccq i/o 6 i/o 7 v ssq i/o 8 v cc l dqm we cas ras cs ba0 ba1 a 10 a 0 a 1 a 2 a 3 v cc v ss i/o 16 v ssq i/o 15 i/o 14 v ccq i/o 13 i/o 12 v ssq i/o 11 i/o 10 v ccq i/o 9 v ss nc udq m clk cke nc a 11 a 9 a 8 a 7 a 6 a 5 a 4 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 clk clock input cke clock enable cs chip select ras row address strobe cas column address strobe we write enable a 0 ?a 11 address inputs ba0, ba1 bank select i/o 1 ?i/o 16 data input/output ldqm, udqm data mask v cc power (+2.5v) v ss ground v ccq power for i/o?s (+1.8v) v ssq ground for i/o?s nc not connected v 55 c 2 12816 4 s x t mosel vitelic manufactured low power synchronous dram c=cmos family 2.5v supply voltage 8mx16(4k refresh) 4 banks s=sttl component rev level component package speed 6 ns 7 ns 8 ns device number a = 0.14um 10 ns description pkg. pin count tsop-ii t 54
4 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) description the v55c2128164v(t/b) is a four bank synchronous dram organized as 4 banks x 2mbit x 16. the v55c2128164v(t/b) achieves high speed data transfer rates up to 166 mhz by employing a chip architecture that prefetches multiple bits and then synch ronizes the output data to a system clock all of the control, address, data input and output circuits are synchronized with the positive edge of an ex- ternally supplied clock. operating the four memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard drams. a sequential and gapless data rate of up to 166 mhz is possible depending on burst length, cas latency and speed grade of the device. signal pin description pin type signal polarity function clk input pulse positive edge the system clock input. all of the sdram inputs are sampled on the rising edge of the clock. cke input level active high activates the clk signal when high and deactivates the clk signal when low, thereby initiates either the power down mode or the self refresh mode. cs input pulse active low cs enables the command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras , cas we input pulse active low when sampled at the positive rising edge of the clock, cas , ras , and we define the command to be executed by the sdram. a0 - a11 input level ? during a bank activate command cycle, a0-a11 defines the row address (ra0-ra11) when sampled at the rising clock edge. during a read or write command cycle, a0-an defines the column address (ca0-can) when sampled at the rising clock edge.can depends from the sdram organization: 8m x 16 sdram ca0?ca8. in addition to the column address, a10(=ap) is used to invoke autoprecharge operation at the end of the burst read or write cycle. if a10 is high, autoprecharge is selected and ba0, ba1 defines the bank to be precharged. if a10 is low, autoprecharge is disabled. during a precharge command cycle, a10(=ap) is used in conjunction with ba0 and ba1 to control which bank(s) to precharge. if a10 is high, all four banks will ba0 and ba1 are used to define which bank to precharge. ba0, ba1 input level ? selects which bank is to be active. dqx input output level ? data input/output pins operate in the same manner as on conventional drams. ldqm udqm input pulse active high the data input/output mask places the dq buffers in a high impedance state when sam- pled high. in read mode, dqm has a latency of two clock cycles and controls the output buffers like an output enable. in write mode, dqm has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if dqm is high. vcc, vss supply power and ground for the input buffers and the core logic. vccq vssq supply ? ? isolated power supply and ground for the output buffers to provide improved noise immunity.
5 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) operation definition all of sdram operations are defined by states of control signals cs , ras , cas , we , and dqm at the positive edge of the clock. the following list shows the thruth table for the operation commands. notes: 1. v = valid , x = don?t care, l = low level, h = high level 2. cken signal is input level when commands are provided, cken-1 signal is input level one clock before the commands are provided. 3. these are state of bank designated by bs0, bs1 signals. 4. power down mode can not entry in the burst cycle. 5. after deep power down mode exit a full new initialization of memory device is mandatory operation device state cke n-1 cke ncs ras cas we dqm a0-9, a11 a10 bs0 bs1 row activate idle 3 hxllhhxvv v read active 3 hxlhlhxvl v read w/autoprecharge active 3 hxlhlhxvh v write active 3 hxlhllxvl v write with autoprecharge active 3 hxlhl lxvh v row precharge any h x l l h l x x l v precharge all any h x l l h l x x h x mode register set idle h x l l l l x v v v no operation any h x l h h h x x x x device deselect any h x h x x x x x x x auto refresh idle h h l l l h x x x x self refresh entry idle h l l l l h x x x x self refresh exit idle (self refr.) l h hxxx xxx x lhhx power down entry idle active 4 hl hxxx xxx x lhhx power down exit any (power down) lh hxxx xxx x lhhl data write/output enable active h x x x x x l x x x data write/output disable active h x x x x x h x x x deep pwoer down entry idle h l l h h l h x x x deep pwoer down exit deep power- down lhxxxxhxx x
6 v55c2128164v(t/b) rev.1.2 august 2002 mosel vitelic v55c2128164v(t/b) power on and initialization the default power on state of the mode register is supplier specific and may be undefined. the following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. like a conventional dram, the synchronous dram must be powered up and initialized in a predefined manner. during power on, all vcc and vccq pins must be built up simultaneously to the specified voltage when the input signals are held in the ?nop? state. the power on voltage must not exceed vcc+0.3v on any of the input pins or vcc supplies. the clk signal must be started at the same time. after power on, an initial pause of 200 s is required followed by a precharge of both banks using the precharge command. to prevent data contention on the dq bus during power on, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been precharged, the mode register and low power mode register set command must be issued to initialize the mode register. a minimum of two auto refresh cycles (cbr) are also required.these may be done before or after programming the mode register. failure to follow these steps may lead to unpredictable start- up modes. programming the mode register the mode register designates the operation mode at the read or write cycle. this register is di- vided into 4 fields. a burst length field to set the length of the burst, an addressing selection bit to program the column access sequence in a burst cy- cle (interleaved or sequential), a cas latency field to set the access time at clock cycle and a opera- tion mode field to differentiate between normal op- eration (burst read and burst write) and a special burst read and single write mode. the mode set operation must be done before any activate com- mand after the initial power up. any content of the mode register can be altered by re-executing the mode set command. all banks must be in pre- charged state and cke must be high at least one clock before the mode set operation. after the mode register is set, a standby or nop command is re- quired. low signals of ras , cas , and we at the positive edge of the clock activate the mode set op- eration. address input data at this timing defines pa- rameters to be set as shown in the previous table. low power mode register the low power mode register controls functions beyond those controlled by the mode register. these additional functions are unique to the low- power drm and includes a refresh period field (tcr) for temperature compensated self-refresh and a partial-array self-refresh field (pas). the pasr field is used to specify whether only one quarter (bank 0), one half (bank 0+1) or all banks of the sdram array are enabled. disabled banks will not be refreshed in self-refresh mode and written data will be lost. when only bank 0 is selected, it?s possible to partially select only half or mone quarter of bank 0. the tcr field has four entries to set re- fresh period during self-refresh depending on the case temperature of the low power ram. it?s re- quired during the initialization seuqence and can be modified when the part id idle. read and write operation when ras is low and both cas and we are high at the positive edge of the clock, a ras cycle starts. according to address data, a word line of the select- ed bank is activated and all of sense amplifiers as- sociated to the wordline are set. a cas cycle is triggered by setting ras high and cas low at a clock timing after a necessary delay, t rcd , from the ras timing. we is used to define either a read (we = h) or a write (we = l) at this stage. sdram provides a wide variety of fast access modes. in a single cas cycle, serial data read or write operations are allowed at up to a 125 mhz data rate. the numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8. column addresses are seg- mented by the burst length and serial data accesses are done within this boundary. the first column ad- dress to be accessed is supplied at the cas timing and the subsequent addresses are generated auto- matically by the programmed burst length and its sequence. for example, in a burst length of 8 with interleave sequence, if the first address is ?2?, then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5.
mosel vitelic v55c2128164v(t/b) 7 v55c2128164v(t/b) rev. 1.2 august 2002 address input for mode set (mode register operation) similar to the page mode of conventional dram?s, burst read or write accesses on any col- umn address are possible once the ras cycle latches the sense amplifiers. the maximum t ras or the refresh interval time limits the number of random column accesses. a new burst access can be done even before the previous burst ends. the interrupt operation at every clock cycles is supported. when the previous burst is interrupted, the remaining ad- dresses are overridden by the new address with the full burst length. an interrupt which accompanies with an operation change from a read to a write is possible by exploiting dqm to avoid bus contention. when two or more banks are activated sequentially, interleaved bank read or write operations are possible. with the programmed burst length, alternate access and precharge operations on two or more banks can realize fast serial data access modes among many different pages. once two or more banks are activated, column to column interleave operation can be done between different pages. a11 a3 a4 a2 a1 a0 a10 a9 a8 a7 a6 a5 address bus (ax) bt burst length cas latency mode register cas latency a6 a5 a4 latency 0 0 0 reserve 001 1 010 2 011 3 1 0 0 reserve 1 0 1 reserve 1 1 0 reserve 1 1 1 reserve burst length a2 a1 a0 length sequential interleave 000 1 1 001 2 2 010 4 4 011 8 8 1 0 0 reserve reserve 1 0 1 reserve reserve 1 1 0 reserve reserve 1 1 1 full page reserve burst type a3 type 0 sequential 1 interleave operation mode ba1 ba0 a11 a10 a9 a8 a7 mode 0000000 burst read/burst write 0000100 burst read/single write operation mode ba0 ba1
8 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) a11 a3 a4 a2 a1 a0 a10 a9 a8 a7 a6 a5 address bus (ax) tcr pasr mode register a4 a3 max case temp 00 70 o c 01 45 o c 10 15 o c 11 85 o c all have to be set to "0" ba0 ba1 partial-array self refresh: a2 a1 a0 banks to be self-refreshed 0 0 0 all banks 0 0 1 1/2 array (ba1=0) 0 1 0 1/4 array (ba1=0, ba0=0) 0 1 1 reserved 1 0 0 reserved 1 0 1 1/8 array (ba1=ba0=0, a11=0) 1 1 0 1/16 array (ba1=ba0=0, a11=a10=0) 1 1 1 reserved 1*) 0*) temperature-compensated self-refresh: *)ba1 and ba0 must be 1, 0 to select the extended mode register (vs. the mode register) the low power mode register must be set during the initialization sequence. once the device is operational, th e low power mode register set can be issued anytime when the part is idle. low power mode register table
9 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) burst length and sequence: refresh mode sdram has two refresh modes, auto refresh and self refresh. auto refresh is similar to the cas -before-ras refresh of conventional drams. all of banks must be precharged before applying any re- fresh mode. an on-chip address counter increments the word and the bank addresses and no bank infor- mation is required for both refresh modes. the chip enters the auto refresh mode, when ras and cas are held low and cke and we are held high at a clock timing. the mode restores word line after the refresh and no external precharge command is necessary. a minimum trc time is re- quired between two automatic refreshes in a burst refresh mode. the same rule applies to any access command after the automatic refresh operation. the chip has an on-chip timer and the self re- fresh mode is available. it enters the mode when ras , cas , and cke are low and we is high at a clock timing. all of external control signals including the clock are disabled. returning cke to high en- ables the clock and initiates the refresh exit opera- tion. after the exit command, at least one t rc delay is required prior to any access command. dqm function dqm has two functions for data i/o read and write operations. during reads, when it turns to ?high? at a clock timing, data outputs are disabled and become high impedance after two clock delay (dqm data disable latency t dqz ). it also provides a data mask function for writes. when dqm is acti- vated, the write operation at the next clock is prohib- ited (dqm write mask latency t dqw = zero clocks). power down in order to reduce standby power consumption, a power down mode is available. all banks must be precharged and the necessary precharge delay (trp) must occur before the sdram can enter the power down mode. once the power down mode is initiated by holding cke low, all of the receiver cir- cuits except clk and cke are gated off. the power down mode does not perform any refresh opera- tions, therefore the device can?t remain in power down mode longer than the refresh period (tref) of the device. exit from this mode is performed by tak- ing cke ?high?. one clock delay is required for mode entry and exit. auto precharge two methods are available to precharge sdrams. in an automatic precharge mode, the cas timing accepts one extra address, ca10, to determine whether the chip restores or not after the operation. if ca10 is high when a read command is issued, the read with auto-precharge function is initiated. the sdram automatically enters the precharge operation one clock before the last data out for cas latencies 2, two clocks for cas laten- cies 3 and three clocks for cas latencies 4. if ca10 is high when a write command is issued, the write a data mask function for writes. when dqm is burst length starting address (a2 a1 a0) sequential burst addressing (decimal) interleave burst addressing (decimal) 2 xx0 xx1 0, 1 1, 0 0, 1 1, 0 4x00 x01 x10 x11 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 8 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 f ull page nnn cn, cn+1, cn+2 not supported
mosel vitelic v55c2128164v(t/b) 10 v55c2128164v(t/b) rev. 1.2 august 2002 with auto-precharge function is initiated. the sdram automatically enters the precharge opera- tion a time delay equal to t wr (write recovery time) after the last data in. precharge command there is also a separate precharge command available. when ras and we are low and cas is high at a clock timing, it triggers the precharge operation. three address bits, ba0, ba1 and a10 are used to define banks as shown in the following list. the precharge command can be imposed one clock before the last data out for cas latency = 2, two clocks before the last data out for cas latency = 3. writes require a time delay twr from the last data out to apply the precharge command. bank selection by address bits: burst termination once a burst read or write operation has been ini- tiated, there are several methods in which to termi- nate the burst operation prematurely. these methods include using another read or write com- mand to interrupt an existing burst operation, use a precharge command to interrupt a burst cycle and close the active bank, or using the burst stop com- mand to terminate the existing burst operation but leave the bank open for future read or write com- mands to the same page of the active bank. when interrupting a burst with another read or write command care must be taken to avoid i/o conten- tion. the burst stop command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. if a burst stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. data that is presented on the i/o pins before the burst stop command is registered will be written to the memory. a10 ba0 ba1 0 0 0 bank 0 0 0 1 bank 1 0 1 0 bank 2 0 1 1 bank 3 1xx all banks recommended operation and characteristics t a = 0 to 70 c(commercial)/-25 to 85 c(extended); v ss = 0 v; v cc = 2.5 v,v ccq = 1.8v note: 1. all voltages are referenced to v ss . 2. v ih may overshoot to v cc + 0.8 v for pulse width of < 4ns with 2.5v. v il may undershoot to -0.8 v for pulse width < 4.0 ns with 2.5v. pulse width measured at 50% points with amplitude measured peak to dc reference. parameter symbol limit values unit notes min. max. supply voltage v cc 2.3 2.9 v i/o supply voltage v ccq 1.65 2.9 v 1, 2 input high voltage v ih 0.8xv ccq vcc+0.3 v 1, 2 input low voltage v il ? 0.3 0.3 v 1, 2 output high voltage (i out = ? 4.0 ma) v oh v ccq -0.2 ? v output low voltage (i out = 4.0 ma) v ol ?0.4v input leakage current, any input (0 v < v in < 3.6 v, all other inputs = 0 v) i i(l) ? 5 5 a output leakage current (dq is disabled, 0 v < v out < v cc ) i o(l) ? 5 5 a deep power down mode thedeep power down mode is an unique functi on with very low standby currents. all internal volat ge generators inside the ram are stopped and all memory data is lost in this mode. to enter the deep power down mode all banks must be precharged.
11 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) absolute maximum ratings* operating temperature range (commercial)0 to 70 c operating temperature range (extended) -25 to 85 c storage temperature range ............... -55 to 150 c input/output voltage .................. -0.3 to (v cc +0.3) v power supply voltage .......................... -0.3 to 3.6 v power dissipation .......................................... 0.7 w data out current (short circuit) ...................... 50 ma *note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. operating currents t a = 0 to 70 c(commercial)/-25 to 85 c(extended); v ss = 0 v; v cc = 2.5 v,v ccq = 1.8v(recommended operating conditions unless otherwise noted) notes: 7. these parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of t ck and t rc . input signals are changed one time during t ck . 8. these parameter depend on output loading. specified values are obtained with output open. symbol parameter & test condition max. unit note -6 -7 / -7pc -8pc 10 icc1 operating current t rc = t rcmin. , t rc = t ckmin . active-precharge command cy- cling, without burst operation 1 bank operation 190 170 150 130 ma 7 icc2p precharge standby current in power down mode cs =v ih , cke v il(max) t ck = min. 1.5 1.5 1.5 1.5 ma 7 icc2ps t ck = infinity 1 1 1 1 ma 7 icc2n precharge standby current in non-power down mode cs =v ih , cke v il(max) t ck = min. 55 45 35 25 ma icc2ns t ck = infinity 5 5 5 5 ma icc3n no operating current t ck = min, cs = v ih(min) bank ; active state ( 4 banks) cke v ih(min.) 65 55 45 35 ma icc3p cke v il(max.) (power down mode) 10 10 10 10 ma icc4 burst operating current t ck = min read/write command cycling 130 110 90 70 ma 7,8 icc5 auto refresh current t ck = min auto refresh command cycling 270 250 210 190 ma 7 icc7 deep power down current 10 10 10 10 ua
12 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) temperature compensated/partial array self-refresh currents parameter & test condition extended mode register m[4:3] tcase[ o c] symb. max. unit self refresh current self refresh mode cke=0.2v, tck=infinity, full array activations, all banks 85 o c max icc6 520 ua 70 o c max 350 ua 45 o c max 250 ua 15 o c max 210 ua self refresh current self refresh mode cke=0.2v, tck=infinity, 1/2 array activations, bank 0+1 85 o c max icc6 380 ua 70 o cmax 250 ua 45 o c max 180 ua 15 o cmax 160 ua self refresh current self refresh mode cke=0.2v, tck=infinity, 1/4 array activations, bank 0 85 o c max icc6 270 ua 70 o c max 180 ua 45 o c max 130 ua 15 o c max 120 ua self refresh current self refresh mode cke=0.2v, tck=infinity, 1/8 array activations, bank 0 85 o c max icc6 190 ua 70 o c max 140 ua 45 o c max 100 ua 15 o c max 90 ua self refresh current self refresh mode cke=0.2v, tck=infinity, 1/16 array activations, bank 0 85 o c max icc6 130 ua 70 o c max 110 ua 45 o c max 90 ua 15 o c max 80 ua
13 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) ac characteristics 1,2, 3 t a = 0 to 70 c(commercial)/-25 to 85 c(extended);v ss = 0 v; v cc = 2.5 v,v ccq = 1.8v, t t =1 ns # symbol parameter limit values unit note -6 -7pc -7 -8pc -10 min. max. min. max. min. max. min. max. min. max. clock and clock enable 1t ck clock cycle time cas latency = 3 cas latency = 2 cas latency = 1 6 7.5 20 ? ? ? 7 7.5 20 ? ? ? 7 10 20 ? ? ? 8 10 20 ? ? ? 10 12 25 ? ? ? ns ns ns 2t ck clock frequency cas latency = 3 cas latency = 2 cas latency = 1 ? ? ? 166 133 50 ? ? ? 143 133 50 ? ? ? 143 100 50 ? ? ? 125 100 50 ? ? ? 100 83 40 mhz mhz mhz 3t ac access time from clock cas latency = 3 cas latency = 2 cas latency = 1 ? _ _ 5.4 5.4 19 ? _ _ 5.4 5.4 19 ? _ _ 5.4 6 19 ? _ _ 6 6 19 ? _ _ 7 8 22 ns ns ns 2, 4 4t ch clock high pulse width 2.5 ? 2.5 ? 2.5 ? 3 ? 3 ? ns 5t cl clock low pulse width 2.5 ? 2.5 ? 2.5 ? 3 ? 3 ? ns 6t t transition tim 0.3 1.2 0.3 1.2 0.3 1.2 0.5 10 0.5 10 ns setup and hold times 7t is input setup time 1.5 ? 1.5 ? 1.5 ? 2 ? 2.5 ? ns 5 8t ih input hold time 0.8 ? 0.8 ? 0.8 ? 1 ? 1 ? ns 5 9t cks input setup time 1.5 ? 1.5 ? 1.5 ? 2 ? 2.5 ? ns 5 10 t ckh cke hold time 0.8 ? 0.8 ? 0.8 ? 1 ? 1 ? ns 5 11 t rsc mode register set-up time 12 ? 14 ? 14 ? 16 ? 20 ? ns 12 t sb power down mode entry time 0 6 0 7 0 7 0 8 0 8 ns common parameters 13 t rcd row to column delay time 12 ? 15 ? 15 ? 20 ? 20 ? ns 6 14 t rp row precharge time 15?15?15? 20 ? 20 ? ns 6 15 t ras row active time 40 100k 42 100k 42 100k 45 100k 50 100k ns 6 16 t rc row cycle time 60?60?60? 60 ? 70 ? ns 6 17 t rrd activate(a) to activate(b) command period 12?14?14? 16 ? 20 ? ns 6 18 t ccd cas (a) to cas (b) command period 1 ? 1 ? 1 ? 1 ? 1 ? clk refresh cycle
14 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) notes for ac parameters: 1. for proper power-up see the operation section of this data sheet. 2. ac timing tests are referenced to the 0.9v crossover point for vccq=1.8v components. the transition time is mea- sured between v ih and v il . all ac measurements assume t t = 1ns with the ac output load circuit shown in figure 1. 4. if clock rising time is longer than 1 ns, a time (t t /2 ? 0.5) ns has to be added to this parameter. 5. if t t is longer than 1 ns, a time (t t ? 1) ns has to be added to this parameter. 6. these parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycle = specified value of timing period (counted in fractions as a whole number) self refresh exit is a synchronous operation and begins on the 2nd positive clock edge after cke returns high. self refresh exit is not complete until a time period equal to trc is satisfied once the self refresh exit command is registered. 7. referenced to the time which the output achieves the open circuit condition, not to output voltage levels 19 t ref refresh period (4096 cycles) ? 64 ? 64 ? 64 ? 64 ? 64 ms 20 t srex self refresh exit time 1 ? 1 ? 1 ? 1 ? 1 ? clk read cycle 21 t oh data out hold time 3?3?3? 3 ? 3 ? ns2 22 t lz data out to low impedance time 1 ? 1 ? 1 ? 1 ? 1 ? ns 23 t hz data out to high impedance time 3 6 3 7 3 7 3 7 3 7 ns 7 24 t dqz dqm data out disable latency ? 2 ? 2 ? 2 ? 2 ? 2 clk write cycle 25 t wr write recovery time 1?1?1? 1 ? 1 ?clk 26 t dqw dqm write mask latency 0 ? 0 ? 0 ? 0 ? 0 ? clk # symbol parameter limit values unit note -6 -7pc -7 -8pc -10 min. max. min. max. min. max. min. max. min. max. 1.4v 1.4v tcs tch tac tac tlz toh thz clk command output 50 pf i/o z=50 ohm + 1.4 v 50 ohm vih vil t t figure 1. tck ac characteristics (cont?d)
15 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) timing diagrams 1. bank activate command cycle 2. burst read operation 3. read interrupted by a read 4. read to write interval 4.1 read to write interval 4.2 minimum read to write interval 4.3 non-minimum read to write interval 5. burst write operation 6. write and read interrupt 6.1 write interrupted by a write 6.2 write interrupted by read 7. burst write & read with auto-precharge 7.1 burst write with auto-precharge 7.2 burst read with auto-precharge 8. burst termination 8.1 termination of a burst write operation 8.2 termination of a burst write operation 9. ac- parameters 9.1 ac parameters for a write timing 9.2 ac parameters for a read timing 10. mode register set 11. power on sequence and auto refresh (cbr) 12. power down mode 13. self refresh (entry and exit) 14. auto refresh (cbr)
16 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) timing diagrams (cont?d) 15. random column read ( page within same bank) 15.1 cas latency = 2 15.2 cas latency = 3 16. random column write ( page within same bank) 16.1 cas latency = 2 16.2 cas latency = 3 17. random row read ( interleaving banks) with precharge 17.1 cas latency = 2 17.2 cas latency = 3 18. random row write ( interleaving banks) with precharge 18.1 cas latency = 2 18.2 cas latency = 3 19. precharge termination of a burst 19.1 cas latency = 2 19.2 cas latency = 3
17 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) 1. bank activate command cycle (cas latency = 3) 2. burst read operation (burst length = 4, cas latency = 2, 3) a ddress c lk t0 t t1 t ttt command nop nop nop bank a row addr. bank a activate write a with auto bank a col. addr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bank b activate bank a row addr. bank a activate t rcd : ?h? or ?l? t rc precharge t rrd bank b row addr. c ommand read a nop nop nop nop nop nop nop dout a 0 c as latency = 2 t ck3, i/o?s c as latency = 3 dout a 1 dout a 2 dout a 3 nop c lk t0 t2 t1 t3 t4 t5 t6 t7 t8 t ck2, i/o?s dout a 0 dout a 1 dout a 2 dout a 3
18 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) 3. read interrupted by a read (burst length = 4, cas latency = 2, 3) 4.1 read to write interval (burst length = 4, cas latency = 3) c ommand read a read b nop nop nop nop nop nop t ck2, i/o?s c as latency = 2 t ck3, i/o?s c as latency = 3 nop c lk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 command nop read a nop nop nop nop write b nop nop dqm dout a 0 din b 0 din b 1 din b 2 must be hi-z before the write command i/o?s minimum delay between the read and write commands = 4+1 = 5 cycles clk t0 t2 t1 t3 t4 t5 t6 t7 t8 t dqz t dqw : ?h? or ?l?
19 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) 4.2 minimum read to write interval (burst length = 4, cas latency = 2) 4.3 non-minimum read to write interval (burst length = 4, cas latency = 2, 3) command nop bank a nop read a write a nop nop nop dqm din a 0 din a 1 din a 2 din a 3 must be hi-z before the write command t ck2, i/o?s cas latency = 2 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 nop activate 1 clk interval t dqz t dqw : ?h? or ?l? nop read a nop nop read a nop write b nop nop dqm din b 0 din b 1 din b 2 t ck1, i/o?s cas latency = 2 t ck2, i/o?s cas latency = 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 0 c ommand din b 0 din b 1 din b 2 dout a 1 dout a 0 must be hi-z before the write command t dqz t dqw : ?h? or ?l?
20 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) 5. burst write operation (burst length = 4, cas latency = 2, 3) 6.1 write interrupted by a write (burst length = 4, cas latency = 2, 3) c ommand nop write a nop nop nop nop nop nop i/o?s din a 0 din a 1 din a 2 din a 3 nop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 extra data is ignored after the first data element and the write are registered on the same clock edge. termination of a burst. don?t care command nop write a write b nop nop nop nop nop i/o?s din a 0 din b 0 din b 1 din b 2 nop din b 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 1 clk interval
21 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) 6.2 write interrupted by a read (burst length = 4, cas latency = 2, 3) 7. burst write with auto-precharge burst length = 2, cas latency = 2, 3) c ommand nop write a read b nop nop nop nop nop nop t ck2, i/o?s c as latency = 2 din a 0 t ck3, i/o?s c as latency = 3 din a 0 c lk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout b 3 dout b 0 dout b 1 dout b 2 dout b 3 don?t care don?t care don?t care dout b 0 dout b 1 dout b 2 input data must be removed from the i/o?s at least one clock cycle before the read dataappears on the outputs to avoid data contention. command nop nop nop write a auto-precharge clk t0 t2 t1 t3 t4 t5 t6 t7 t8 nop bank a active nop nop din a 0 din a 1 i/o?s cas latency = 3 i/o?s cas latency = 2 begin autoprecharge bank can be reactivated after trp * t wr t rp din a 0 din a 1 t wr t rp nop *
22 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) 7.2 burst read with auto-precharge burst length = 4, cas latency = 2, 3) c ommand read a nop nop nop nop nop nop t ck2, i/o?s c as latency = 2 t ck3, i/o?s c as latency = 3 c lk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 3 dout a t rp t rp * * * 0 dout a 1 dout a 2 dout a 3 dout a begin autoprecharge bank can be reactivated after t rp 0 dout a 1 dout a 2 nop nop
23 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) 8.1 termination of a burst read operation (cas latency = 2, 3) 8.2 termination of a burst write operation (cas latency = 2, 3) command read a nop nop nop burst nop nop nop nop t ck2, i/o?s cas latency = 2 t ck3, i/o?s cas latency = 3 stop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 command nop write a nop nop burst nop nop nop nop din a 0 din a 1 din a 2 stop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 input data for the write is masked. i/o?s cas latency = 2,3 don?t care
24 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) clk cke cs i/o ras cas we ba dqm 9.1 ac parameters for write timing t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 2 addr t cks t cs t ch t ckh t as t rcd t rc t rp t ds activate command bank a write with auto precharge command bank a activate command bank b write with auto precharge command bank b activate command bank a write command bank a precharge command bank a activate command bank a t dh ax0 ax3 ax2 ax1 bx0 bx3 bx2 bx1 ay0 ay3 ay2 ay1 t ck2 t ch t cl begin auto precharge bank a begin auto precharge bank b t dpl t rrd activate command bank b ray cbx ray ray rbx rbx cax rby rby raz raz rax rax t ah
25 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) \ clk cke cs i/o ras cas we ba dqm 9.2 ac parameters for read timing t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t10 hi-z ap burst length = 2, cas latency = 2 addr t cs t ch t ckh t as t ah t rrd t rcd t ras t lz activate command bank a activate command bank b activate command bank a precharge command bank a t cks t ck2 ax0 ax1 read command bank a read with auto precharge command bank b t rc t rp t ac2 t ac2 t oh t hz t ch t cl bx0 begin auto precharge bank b bx1 t hz rbx ray rbx rbx ray cax rax rax
26 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) \ 10. mode register set clk cke cs ras cas we ba t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 ap addr precharge command all banks mode register set command any command address key 2 clock min.
27 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) \ 11. power on sequence and auto refresh (cbr) clk cke cs i/o ras cas we ba dqm ttt t0 tt t tt t t t tt t1 t t tt ttt t hi-z ap addr precharge command all banks t rp minimum of 2 refresh cycles are required 1st auto refresh command t rc high level is required 2nd auto refresh command inputs must be stable for 200 s low power mode register set command 2 clock min. mode register address key set command
28 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) \ 12. power down mode burst length = 4, cas latency = 2 clk cke cs i/o ras cas we ba dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr t cksp rax rax activate command bank a precharge command bank a power down mode entry power down mode exit any command
29 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) 13. self refresh (entry and exit) ba addr ap t clk cke cs i/o ras cas we d qm t2 t3 t4 t0 t1 t t tt t5 t t tt t t t tt tt t t hi-z all banks must be idle self refresh entry begin self refresh exit command t srex self refresh exit command issued self refresh exit t rc cksr
30 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) \ 14. auto refresh (cbr) burst length = 4, cas latency = 2 clk cke cs i/o ras cas we ba dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr ax0 ax1 activate command read command precharge command auto refresh command auto refresh command t rc t rp t rc t ck2 all banks cax rax rax bank a bank a ax2 ax3 (minimum interval)
31 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) \ ) 15.1 random column read (page within same bank) (1 of 2) burst length = 4, cas latency = 2 clk cke cs i/o ras cas we ba dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr activate command bank a cax read command bank a cay read command bank a aw0 aw1 aw2 aw3 ax0 ax1 ay0 ay1 az0 az1 az2 az3 ay2 ay3 caw read command bank a raw raw precharge command bank a activate command bank a caz read command bank a raz raz t ck2
32 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) \ ) 15.2 random column read (page within same bank) (2 of 2) burst length = 4, cas latency = 3 clk cke cs i/o ras cas we ba d qm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr activate command bank a cax read command bank a cay read command bank a aw0 aw1 aw2 aw3 ax0 ax1 ay0 ay1 ay2 ay3 caw read command bank a raw raw precharge command bank a activate command bank a caz read command bank a raz raz t ck3
33 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) \ ) 16.1 random column write (page within same bank) (1 of 2) burst length = 4, cas latency = 2 clk cke cs i/o ras cas we ba dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr cbx write command bank b cby write command bank b precharge command bank b dbw0 dbw3 dbw2 dbw1 dbx1 dbx0 dby0 dby3 dby2 dby1 dbz0 dbz3 dbz2 dbz1 t ck2 activate command bank b cax write command bank b raw raw activate command bank b cbz write command bank b rbz rbz activate command bank b cbz write command bank b rbz rbz
34 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) \ ) 16.2 random column write (page within same bank) (2 of 2) burst length = 4, cas latency = 3 clk cke cs i/o ras cas we ba dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr cbx write command bank b cby write command bank b precharge command bank b dbw0 dbw3 dbw2 dbw1 dbx1 dbx0 dby0 dby3 dby2 dby1 dbz0 dbz1 t ck3 activate command bank b cbz write command bank b rbz rbz activate command bank b cbz write command bank b rbz rbz
35 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) 17.1 random row read (interleaving banks) (1 of 2) burst length = 8, cas latency = 2 clk cke cs i/o ras cas we a11(bs) dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0 - a9 cby read command bank b read command bank a bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 by0 by1 t ck2 high t rcd t ac2 t rp cax precharge command bank b ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 activate command bank b rbx rbx activate command bank a rax rax cbx read command bank b activate command bank b rby rby
36 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) 17. 2 random row read (interleaving banks) (2 of 2) burst length = 8, cas latency = 3 clk cke cs i/o ras cas we a 11(bs) dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0 - a9 cby read command bank b by0 t ck3 high t ac3 activate command bank b rbx rbx activate command bank a rax rax cbx read command bank b activate command bank b rby rby t rcd precharge command bank b cax read command bank a t rp bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 precharge command bank a
37 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) 18.1 random row write (interleaving banks) (1 of 2) burst length = 8, cas latency = 2 clk cke cs i/o ras cas we a 11(bs) dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0 - a9 t ck2 high t rcd t rp write command bank a cay dax0 dax3 dax2 dax1 dax4 dax7 dax6 dax5 dbx0 dbx3 dbx2 dbx1 dbx4 dbx7 dbx6 dbx5 day0 day3 day2 day1 t dpl write command bank a cax activate command bank a rax rax activate command bank b rbx rbx cbx precharge command bank a write command bank b activate command bank a ray ray cay precharge command bank b write command bank a day4 t dpl
38 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) 18.2 random row write (interleaving banks) (2 of 2) burst length = 8, cas latency = 3 clk cke cs i/o ras cas we a11(bs) dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0 - a9 t ck3 high dax0 dax3 dax2 dax1 dax4 dax7 dax6 dax5 dbx0 dbx3 dbx2 dbx1 dbx4 dbx7 dbx6 dbx5 day2 day1 day0 write command bank a cax activate command bank b rbx rbx activate command bank a ray ray day3 t dpl cbx write command bank b precharge command bank a write command bank a cay precharge command bank b t rp t dpl t rcd activate command bank a rax rax
39 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) 19.1 precharge termination of a burst (1 of 2) burst length = 8, cas latency = 2 clk cke cs i/o ras cas we ba dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr t ck2 precharge command bank a dax0 dax3 dax2 dax1 precharge termination of a write burst. write data is masked. ay0 ay1 ay2 precharge termination of a read burst. precharge command bank a t rp activate command bank a rax rax write command bank a cax cay read command bank a high activate command bank a ray ray t rp activate command bank a raz raz caz read command bank a az0 az1 az2 precharge command bank a t rp
40 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) 19.2 precharge termination of a burst (2 of 2) burst length = 4, 8, cas latency = 3 clk cke cs i/o ras cas we ba d qm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr t ck3 precharge command bank a dax0 precharge termination of a write burst. write data is masked ay0 ay1 ay2 precharge termination precharge command bank a t rp activate command bank a rax rax write command bank a cax cay read command bank a high activate command bank a ray ray t rp activate command bank a raz raz of a read burst.
41 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) 20.1 deep power down mode entry the deep power down mode has to be maintained for a minimum of 100s. clk cke cs we cas ras addr. dqm dq input dq output high-z t rp precharge command deep power down entry deep power down mode dp1.vsd normal mode
42 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) 20.2 deep power down exit the deep power down mode is exited by asserting cke high. after the exit, the following sequence is needed to enter a new command: 1. maintain nop input conditions for a minimum of 200 s 2. issue precharge commands for all banks of the device 3. issue eight or more autorefresh commands 4. issue a mode register set command to initialize the mode register 5. issue an extended mode register set command to initialize the extende mode register clk ck e cs ra s ca s we trp all banks 200 s au to deep power do wn auto trc mode exi t prec harge refresh refresh register set exte nded mode regis ter set new com mand acce pted here
43 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) fbga-boc package 54 bga package with 3 depop. rows
44 v55c2128164v(t/b) rev. 1.2 august 2002 mosel vitelic v55c2128164v(t/b) worldwide offices ? copyright , mosel vitelic corp. printed in u.s.a. the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality contr ol sampling techniques which are intended to provide an assuranc e of high quality products suitable for usual commercial applica - tions. mosel vitelic does not do testing appropriate to provid e 100% product quality assurance and does not assume any liab il- ity for consequential or incidental arising from any use of its prod - ucts. if such products are to be used in applications in whic h personal injury might occur from failure, purchaser must do i ts own quality assurance testing appropriate to such applications. u.s. sales offices u .s.a. 3 910 north first street s an jose, ca 95134 p hone: 408-433-6000 fax: 408-433-0952 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 886-2-2545-1213 fax: 886-2-2545-1209 no 19 li hsin road science based ind. park hsin chu, taiwan, r.o.c. phone: 886-3-579-5888 fax: 886-3-566-5888 singapore 10 anson road #23-13 international plaza singapore 079903 phone: 65-6323-1801 fax: 65-6323-7013 japan onze 1852 building 6f 2-14-6 shintomi, chuo-ku tokyo 104-0041 phone: 03-3537-1400 fax: 03-3537-1402 uk & ireland suite 50, grovewood business centre strathclyde business park bellshill, lanarkshire, scotland, ml4 3nq phone: 44-1698-748515 fax: 44-1698-748516 w est 3 910 north first street s an jose, ca 95134 p hone: 408-433-6000 fax: 408-433-0952 central / east 604 fieldwood circle richardson, tx 75081 phone: 214-352-3775 fax: 214-904-9029

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